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HB52F168GB-B HB52D168GB-B
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Description Features
128 MB Unbuffered SDRAM Micro DIMM 16-Mword x 64-bit, 133/100 MHz Memory Bus, 1-Bank Module (4 pcs of 16 M x 16 components) PC133/100 SDRAM
The HB52F168GB and HB52D168GB are a 16M x 64 x 1 banks Synchronous Dynamic RAM Micro Dual In-line Memory Module (Micro DIMM), mounted 4 pieces of 256-Mbit SDRAM (HM5225165BTT) sealed in TSOP package and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside TSOP on the module board.
* 144-pin Zig Zag Dual tabs socket type (dual lead out) Outline: 38.00 mm (Length) x 30.00 mm (Height) x 3.80 mm (Thickness) Lead pitch: 0.50 mm * 3.3 V power supply * Clock frequency: 133/100 MHz (max) * LVTTL interface * Data bus width: x 64 Non parity * Single pulsed RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length: 1/2/4/8 * 2 variations of burst sequence Sequential Interleave
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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E0008H10 (1st edition) (Previous ADE-203-1219A (Z)) Jan. 19, 2001
This product became EOL in September, 2002.
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HB52F168GB-B, HB52D168GB-B
* * * * Programmable CE latency: 2/3 Byte control by DQMB Refresh cycles: 8192 refresh cycles/64 ms 2 variations of refresh Auto refresh Self refresh * Low self refresh current : HB52F168GB-xxBL : HB52D168GB-xxBL
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Type No. HB52F168GB-75B* HB52F168GB-75BL* 1
1
Ordering Information
Frequency CE latency 3 3 2/3 2/3 3 3 Package Micro DIMM (144-pin) Contact pad Gold
HB52D168GB-A6B HB52D168GB-A6BL HB52D168GB-B6B* 2 HB52D168GB-B6BL* 2
Notes: 1. 100 MHz operation at CE latency = 2. 2. 66 MHz operation at CE latency = 2.
Pin Arrangement
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133 MHz 133 MHz 100 MHz 100 MHz 100 MHz 100 MHz
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Front Side
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143pin 144pin
1pin 2pin
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Back Side
Data Sheet E0008H10 2
HB52F168GB-B, HB52D168GB-B
Front side Pin No. 1 3 5 7 9 Signal name Pin No. VSS 73 75 77 79 81 83 85 87 89 91 Back side Signal name Pin No. NC VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC A6 A8 2 4 6 8 10 12 14 16 18 20 22 24 26 28 Signal name Pin No. VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VCC 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 Signal name CK1 VSS NC NC VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VCC A7 BA0 VSS BA1 A11 VCC DQMB6 DQMB7 VSS DQ56 DQ57 DQ58
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DQ0 DQ1 DQ2 DQ3 VCC 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC
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93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131
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30 32 34 VSS A9 36 38 A10 (AP) VCC DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 40 42 44 46 48 50 52 54 56 58 60 Data Sheet E0008H10
A3 A4 A5
VSS DQ40 DQ41
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DQ42 114 DQ43 116 VCC 118 DQ44 120 DQ45 DQ46 DQ47 VSS NC NC 122 124 126 128 130 132
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DQ59 VCC DQ60 3
HB52F168GB-B, HB52D168GB-B
Front side Pin No. 61 63 65 67 69 71 Signal name Pin No. CK0 VCC 133 135 137 139 141 143 Back side Signal name Pin No. DQ29 DQ30 DQ31 VSS SDA VCC 62 64 66 68 70 72 Signal name Pin No. CKE0 VCC CE NC A12 NC 134 136 138 140 142 144 Signal name DQ61 DQ62 DQ63 VSS SCL VCC
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RE W S0 NC
Pin Description
Pin name A0 to A12
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Function Address input Row address A0 to A12 Column address A0 to A8 Bank select address Data-input/output
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Chip select Write enable Byte input/output mask Clock input Clock enable Power supply Ground No connection Data Sheet E0008H10
BA0/BA1 DQ0 to DQ63 S0 RE CE W DQMB0 to DQMB7 CK0/CK1 CKE0 SDA SCL VCC VSS NC
Row address asserted bank enable Column address asserted
Data-input/output for serial PD Clock input for serial PD
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4
HB52F168GB-B, HB52D168GB-B
Serial PD Matrix*1
Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 80 08 04 0D 09 01 40 00 01 75 128 256 byte SDRAM 13 9 1 64 0 (+) LVTTL CL = 3
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0 1 2 3 4 5 6 7 8 9 Memory type 10 (-A6/B6) 6 ns 11 12 13 14 15 SDRAM width 16 17 18 19
Number of bytes used by module manufacturer Total SPD memory size
Number of row addresses bits 0 0 0 0
Number of column addresses bits Number of banks Module data width
Module data width (continued) 0 Module interface signal levels 0 SDRAM cycle time (highest CE latency) (-75) 7.5 ns (-A6/B6) 10 ns 0
SDRAM access from Clock (highest CE latency) (-75) 5.4 ns
Module configuration type Refresh rate/type
Error checking SDRAM width
0 SDRAM device attributes: minimum clock delay for backto-back random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: CE latency SDRAM device attributes: S latency 0 0
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1 0 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Data Sheet E0008H10
0
0 0
0 0
A0 54
1
0 0 0
0 0 1
0 0 0
60 00 82 Non parity Normal (7.8125 s) Self refresh x 16 -- 1 CLK
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0 0 0 0 0 0 10 00 0 0 1 01 1 1 1 0 1 0 0F 04 1 0 1 0 0 1 06 01
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1, 2, 4, 8 4 2, 3 0 5
HB52F168GB-B, HB52D168GB-B
Byte No. Function described 20 21 22 23 SDRAM device attributes: W latency SDRAM module attributes Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 01 00 0E A0 0 Unbuffer VCC 10% CL = 2
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(-B6) 15 ns 24 (-B6) 8 ns 25 26 27 28 (-A6/B6) 29 30 (-A6/B6) 31 32 (-A6/B6) 33 (-A6/B6) 34 (-A6/B6) 6
SDRAM device attributes: General SDRAM cycle time (2nd highest CE latency) (-75/A6) 10 ns
1 0
1 1
1 1
1 0
0 0
0 0
0 0
0 0
F0 60
SDRAM access from Clock (2nd highest CE latency) (-75/A6) 6 ns
SDRAM cycle time (3rd highest CE latency) Undefined
SDRAM access from Clock (3rd highest CE latency) Undefined
Minimum row precharge time Row active to row active min (-75)
RE to CE delay min
Minimum RE pulse width (-75)
Density of each bank on module
Address and command signal 0 input setup time (-75) 0
Address and command signal 0 input hold time (-75) 0 0 0
Data signal input setup time (-75)
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1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
80 00
0
0
0
0
0
0
0
0
00
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0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 Data Sheet E0008H10
1
0 1 0 0
0 1 0 0
14 0F 14 14
20 ns 15 ns 20 ns 20 ns 45 ns 50 ns 128M byte 1.5 ns
1 1
1
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1 0 1 0 1 0 32 0 1 0 0 0 1 20 15 0 0 0 0 20 0 0 08 0 1 0 0 0 10 0 1 15 0 0 20
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2.0 ns 0.8 ns 1.0 ns 1.5 ns 2.0 ns
HB52F168GB-B, HB52D168GB-B
Byte No. Function described 35 Data signal input hold time (-75) (-A6/B6) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 0 1 0 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 1 0 0 0 0 0 0 1 1 0 0 0 x 0 0 1 1 0 1 0 1 1 0 1 0 0 x 0 0 1 1 1 0 0 0 1 0 0 0 0 x 1 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 1 0 0 0 0 1 0 0 0 1 0 x 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 0 1 0 0 1 0 x 0 0 1 0 0 0 1 0 0 1 0 1 08 10 00 12 39 A0 10 07 00 xx 48 42 35 32 46 44 31 36 38 47 42 * 2 (ASCII8bit code) H B 5 2 F D 1 6 8 G B -- 7 A B 0.8 ns 1.0 ns Future use Rev. 1.2B 57 160 16 HITACHI
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62 63 (-A6) (-B6) 64 72 73 74 75 76 77 (-A6/B6) 78 79 80 81 82 83 84 (-A6) (-B6) 85 (-A6/B6) 86 87 88
36 to 61 Superset information SPD data revision code Checksum for bytes 0 to 62 (-75)
Manuf act urer's JEDEC ID c ode
65 to 71 Manuf act urer's JEDEC ID c ode Manufacturing location
Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (-75)
Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (-75)
Manufacturer's part number (-75)
Manufacturer's part number Manufacturer's part number (L-version) Manufacturer's part number Manufacturer's part number
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0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 Data Sheet E0008H10
1 1 0 1 0 1 0 1
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1 1 1 37 0 0 1 1 0 1 0 0 0 1 1 0 41 42 0 1 35 1 0 36 1 0 42 0 0 0 0 20 0 0 20
2D
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5 6 B 4C L (Space) (Space) 7
HB52F168GB-B, HB52D168GB-B
Byte No. Function described 89 90 91 92 93 94 Manufacturer's part number Manufacturer's part number Revision code Revision code Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 x x *3 -- 0 -- 1 1 -- 1 0 -- 0 0 -- 0 0 -- 1 1 -- 0 1 -- 0 1 -- 64 C7 *4 100 MHz CL = 2, 3 0 0 0 0 x x 1 1 1 1 x x 0 0 1 0 x x 0 0 0 0 x x 0 0 0 0 x x 0 0 0 0 x x 0 0 0 0 x x 20 20 30 20 xx xx (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD)
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126 127 (-B6) 8
Manufacturing date Manufacturing date
95 to 98 Assembly serial number 99 to 125 Manufacturer specific data Intel specification frequency
Intel specification CE# latency 1 support (-75/A6) 1
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on Rev. 1.2B Specification. 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 125 are not defined ("1" or "0").
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1
0
0
0
1
0
1
C5
CL = 3
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Data Sheet E0008H10
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HB52F168GB-B, HB52D168GB-B
Block Diagram
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RE CE A0 to A12 BA0 BA1 CKE0 CK0 R0 CK1 VCC
C0-C7
S0 W CS 8 N0, N1 DQ32 to DQ39 DQMB4 8 N8, N9 CS
DQMB0
DQ0 to DQ7
D0
DQMB5 8 N2, N3 DQ40 to DQ47 CS CS 8 N12, N13 DQ48 to DQ55 8 N10, N11
D2
DQMB1
DQ8 to DQ15
DQ16 to DQ23
DQ24 to DQ31
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DQMB2 DQMB3 C200
C100-C103
DQMB6
8 N4, N5
D1
DQMB7 8 N14, N15 DQ56 to DQ63
D3
8 N6, N7
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RAS (D0 to D3) CAS (D0 to D3) A0 to A12 (D0 to D3) BA0 (D0 to D3) BA1 (D0 to D3) CKE (D0 to D3) CLK (D0) CLK (D1) CLK (D2) CLK (D3) VCC (D0 to D3, U0) VSS (D0 to D3, U0) Data Sheet E0008H10
Serial PD SCL A0 A1 A2 U0 SDA SDA
SCL
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VSS Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
* D0 to D3: HM5225165 U0: 2-kbit EEPROM C0 to C7: 0.33 F C100 to C103: 0.1 F C200: 10 pF N0 to N15: Network resistors (10 ) R0: Resistor (10 )
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VSS
HB52F168GB-B, HB52D168GB-B
Absolute Maximum Ratings
Parameter Symbol VT VCC Iout PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 4.0 0 to +65 -55 to +125 Unit V V mA W C C Note 1 1
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Power dissipation Operating temperature Storage temperature Note: Parameter Supply voltage Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5. 10
Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current
1. Respect to V SS .
DC Operating Conditions (Ta = 0 to +65C)
Symbol VCC VSS VIH VIL Min 3.0 0 Max 3.6 0 VCC + 0.3 0.8 Unit V V V V Notes 1, 2 3 1, 4 1, 5
All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC. VIL (min) = VSS - 2.0 V for pulse width 3 ns at VSS .
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2.0 -0.3 Data Sheet E0008H10
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HB52F168GB-B, HB52D168GB-B
DC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HB52F168GB-B/HB52D168GB-B
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Parameter Operating current (CE latency = 2) (CE latency = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current (CE latency = 2) (CE latency = 3) Refresh current Self refresh current Self refresh current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
-75 Symbol Min I CC1 I CC1 I CC2P I CC2PS I CC2N I CC3P -- -- -- -- -- -- -- -- -- -- -- -- -10 -10 2.4 -- Max 400 460 12 8 80 16 120 440 580 880 12 8
-A6/B6 Min -- Max 400 400 -- -- -- -- -- -- 12 8 80 16 120 440 440 Unit Test conditions mA mA mA mA mA mA mA mA mA mA mA mA A A t RC = min VIH VCC - 0.2 V VIL 0.2 V 3 8 CKE0 = VIL, t CK = 12 ns CKE0 = VIL, t CK = CKE0, S = VIH, t CK = 12 ns CKE0, S = VIH, t CK = 12 ns CKE0, S = VIH, t CK = 12 ns t CK = min, BL = 4 6 7 4 1, 2, 6 1, 2, 4 1, 2, 5 Burst length = 1 t RC = min Notes 1, 2, 3
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK0/CK1 operating current. 7. After power down mode, no CK0/CK1 operating current. 8. After self refresh mode set, self refresh current.
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I CC3N I CC4 I CC4 I CC5 I CC6 I CC6 I LI I LO VOH VOL
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-- -- -- 12 8 10 10 -- -10 -10 2.4 -- 10 10 -- 0.4 Data Sheet E0008H10
880
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V 0.4 V
0 Vin VCC
0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA
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11
HB52F168GB-B, HB52D168GB-B
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Symbol CIN CIN CIN CIN CI/O Max 40 40 40 20 20 Unit pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
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Input capacitance (S0) Notes: 1. 2. 3. 4. 12
Input capacitance (Address) Input capacitance (RE, CE, W, CK0/CK1, CKE0)
Input capacitance (DQMB0 to DQMB7) Input/Output capacitance (DQ0 to DQ63)
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested.
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Data Sheet E0008H10
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HB52F168GB-B, HB52D168GB-B
AC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HB52F168GB-B/HB52D168GB-B -75 Symbol t CK t CK t CKH t CKH PC100 Symbol Min Tclk Tclk Tch Tch Tcl Tcl 10 7.5 3 2.5 3 2.5 -- -- 3 Max -- -- -- -- -- -- 6 5.4 -- -- -A6 Min 10 10 3 3 3 3 -- -- 3 3 Max -- -- -- -- -- -- 6 6 -- -- -- 6 -B6 Min 15 10 3 3 3 3 -- -- 3 3 2 -- Max -- -- -- -- -- -- 8 6 -- -- -- 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2 1, 2, 3 1, 4 1, 2 1 1 Notes 1
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Parameter System clock cycle time (CE latency = 2) (CE latency = 3) CK high pulse width (CE latency = 2) (CE latency = 3) CK low pulse width (CE latency = 2) (CE latency = 3) Access time from CK (CE latency = 2) (CE latency = 3) Data-out hold time (CE latency = 2) (CE latency = 3) CK to Data-out low impedance CK to Data-out high impedance (CE latency = 2) (CE latency = 3) Data-in setup time (CE latency = 2) (CE latency = 3) CKE setup time for power down exit (CE latency = 2) (CE latency = 3) Data-in hold time (CE latency = 2) (CE latency = 3)
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t CKL t CKL t AC t AC t OH t OH t LZ t HZ t HZ t AS , t CS, t DS, t CES t AS , t CS, t DS, t CES t CESP Tsi Tsi t CESP t AH, t CH, t DH, t CEH t AH, t CH, t DH, t CEH Thi Thi
Tac Tac
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Toh Toh 2.7 2 -- 6 2 -- -- -- 2 1.5 2 5.4 -- -- -- -- 2 2 2 Tpde Tpde 1.5 1 0.8 -- -- -- 2 1 1 Data Sheet E0008H10
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6 -- 2 2 2 6 -- -- -- -- -- -- 2 1 1
ns ns ns ns 1 1, 5, 6
-- -- --
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-- -- -- ns ns ns 1, 5 13
HB52F168GB-B, HB52D168GB-B
HB52F168GB-B/HB52D168GB-B -75 Parameter Symbol t RC PC100 Symbol Min Trc 70 -A6 Max -- Min 70 Max -- -B6 Min 70 Max -- Unit ns Notes 1
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Ref/Active to Ref/Active command period (CE latency = 2) (CE latency = 3) Active to Precharge command period (CE latency = 2) (CE latency = 3) Active command to column command (same bank) Precharge to active command period (CE latency = 3) Active (a) to Active (b) command period (CE latency = 2) (CE latency = 3) Transition time (rise and fall) Refresh period Notes: 1. 2. 3. 4. 5. 14
t RC t RAS
Trc Tras
67.5 50
--
70
--
70
--
ns 1
120000 50
120000 50
120000 ns
t RAS t RCD
Tras Trcd
45 20
120000 50 -- 20
120000 50 -- 20
120000 ns -- ns 1
Write recovery or data-in t DPL to precharge lead time (CE latency = 2) t DPL t RRD
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is C L = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CK rising edge except power down exit command.
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t RP Trp t RRD tT t REF
20 20
-- --
20 20
-- --
20 20
-- --
ns ns
1 1
Tdpl
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Tdpl Trrd 15 20 -- -- 20 20 Trrd 15 -- 20 1 -- 5 1 64 -- Data Sheet E0008H10
-- --
20 20
-- --
ns ns 1
--
20
--
ns ns ms
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5 1 5 64 --
64
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HB52F168GB-B, HB52D168GB-B
Test Conditions * Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures
2.4 V 0.4 V 2.0 V 0.8 V
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input
DQ CL t
T
tT
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Data Sheet E0008H10 15
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HB52F168GB-B, HB52D168GB-B
Relationship Between Frequency and Minimum Latency
HB52F168GB-B/HB52D168GB-B
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Parameter Frequency (MHz) tCK (ns) Self refresh exit time DQMB to data in DQMB to data out CKE to CK disable S to command disable 16
133 CE latency = 3 PC100 Symbol Symbol 7.5 I RCD I RC 3 9 6 3 Tdpl 2 2
100 CE latency = 2 10 2 7 5 2 2 2 1 4 7 2 Notes 1 = [IRAS + IRP] 1 1 1 1 1 2 = [IDPL + IRP] = [IRC] 3
Active command to column command (same bank) Active command to active command (same bank)
Active command to precharge command I RAS (same bank) Precharge command to active command I RP (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) I DPL I RRD
Last data in to active command (Auto precharge, same bank)
Self refresh exit to command input
Precharge command to high impedance Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) Column command to column command Write command to data in latency
Register set to active command
Power down exit to command input
Notes: 1. I RCD to IRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP]
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I SREX Tsrx 1 5 I APW I SEC I HZP I APR I EP I CCD I WCD I DID I DOD I CLE I RSA I CDD I PEC Tdal 9 Troh 3 1 -2 1 0 Tccd Tdwd Tdqm Tdqz Tcke Tmrd 0 2 1 1 0 1 Data Sheet E0008H10
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1 -1 1 0 0 2
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1 1 0 1
HB52F168GB-B, HB52D168GB-B
Pin Functions
CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM modules, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY8) is determined by A0 to A8 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1(BA) is precharged. BA0/BA1 (input pin): BA0/BA1 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If BA0 is Low and BA1 is Low, bank0 is selected. If BA0 is Low and BA1 is High, bank1 is selected. If BA0 is High and BA1 is Low, bank2 is selected. If BA0 is High and BA1 is High, bank3 is selected. CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self refresh mode. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks). Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written (The latency of DQMB during writing is 0 clock). DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.
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Detailed Operation Part
Refer to the SDRAM DIMM Operation Guide.
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Data Sheet E0008H10
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17
HB52F168GB-B, HB52D168GB-B
Physical Outline
15.0
1
A
17.625 35.50
B 0.875
2.5 Min
3.5 Min
37.0 0.08 35.50
17.875
0.625
R1.0 0.1
2
1.0 Min
Detail A
Detail B
4.0 0.1
4-R1.0 0.1
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1.0 Min
3.5 Min 0.80 0.08 0.50
5.0 0.1
1.0 0.08
Data Sheet E0008H10 18
0.25 Max
0.37 0.03
2.00 Min
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1.0 Min 30.0
42.0 Max (38.0) 1.0 Min
Unit: mm 3.80 Max
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HB52F168GB-B, HB52D168GB-B
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
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Data Sheet E0008H10
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